An integrated semiconductor chip includes a large number of electrical elements, such as transistors, capacitors, resistors and so on, and the electrical elements are connected with conductive metal layers of certain patterns to form functional circuits. The size of the integrated semiconductor chip becomes smaller and the functionality thereof becomes being magnified over several generations. To increase the integration degree of the semiconductor chip, the size of the electrical elements may be reduced. However, there is an inherent limitation in reducing the size of the electrical elements. Thus, a multilevel interconnection technology of the electrical elements has been actively studied and developed. In manufacturing a semiconductor device with the multilevel interconnection technology, a planarization process of a metal layer is indispensable. The metal layer is not easily polished due to its relatively high strength, and therefore, the metal layer should be converted into a metal oxide layer having a relatively low strength for effective polishing of the metal layer.
CMP slurry compositions for such polishing of a metal layer were disclosed in Korean Patent Laid-open Nos. 2004-29239, 2004-35073, 2004-35074 and 2004-55042. However, the CMP slurry compositions disclosed in the above-mentioned references have a disadvantage of not providing sufficient chemical conversion of the metal layer into a metal oxide layer. From 1876, Fenton's reagent, which is a composition composed with hydrogen peroxide and iron salt, is conventionally used for oxidizing a metal layer. However, in the method, an excess amount of iron salt, such as Fe(NO3)3 is necessary, and the excess iron salt may badly influences the metal layer to be polished. Accordingly, it is necessary to develop a CMP slurry composition which effectively oxidizes the metal layer and does not produce defects on the polished metal layer.